Transistor with an electron and a vertical channel and production methods thereof

ABSTRACT

This invention relates to a Coulomb blockade transistor comprising the following on a substrate:  
     a stack of channel layers ( 22   c   , 22   i ) forming at least one quantum box,  
     a source ( 12 ) and a drain ( 80 ) connected to the quantum box through tunnel junctions, and stacked with the channel layers,  
     at least one grid ( 60 ) facing at least one flank of the stack.

TECHNICAL FIELD

[0001] This invention relates to a Single Electron Transistor (SET). Italso relates to processes for making such transistors.

[0002] Single electron transistors are also called Coulomb blockadetransistors. They have an extremely thin channel which is like a quantumbox, and which is connected to a source and to a drain through tunneljunctions. The channel conduction is modified significantly depending onwhether or not a weak charge of the order of the charge of one electronis “stored” in the quantum box.

[0003] The invention is generally used in applications in electronicsfields, and particularly for making integrated circuits includingswitching transistor or memory structures.

STATE OF PRIOR ART

[0004] The state of the art according to the invention is illustrated indocuments (1), (2) and (3), that are referenced at the end of thisdescription.

[0005] There are a number of difficulties in making single electrontransistors. One of these difficulties is the difficulty in making asufficiently thin channel. Another difficulty is related to theassociation of the source, drain and grid with the channel.

[0006] The electrical capacitance between firstly the source and thedrain, and secondly the channel must be as low as possible. This isnecessary to enable high operating frequencies of the transistor. On theother hand, the capacitance between the channel and the grid must behigh to give good transistor control.

PRESENTATION OF THE INVENTION

[0007] The purpose of this invention is to propose a Coulomb blockadetransistor and processes for making such a transistor capable ofovercoming the difficulties mentioned above.

[0008] One purpose of the invention is particularly to propose atransistor with weak drain—channel and source—channel junctioncapacitances while guaranteeing a high grid—channel capacitance.

[0009] Another purpose is to propose reliable and reproducible processesfor making the transistor.

[0010] Another purpose of the invention is to propose processes adaptedto collective fabrication of a large number of transistors, possiblyconnected in switching or memory circuits.

[0011] To achieve these purposes, the invention more precisely relatesto Coulomb blockade transistors comprising the following on a substrate:

[0012] a stack of channel layers forming at least one quantum box,

[0013] a source and a drain connected to the quantum box through tunneljunctions, at least one which is distinct from the layers of the stack,and stacked with the channel layers,

[0014] at least one grid facing at least one flank of the stack.

[0015] According to one characteristic of the transistor, the stack ofchannel layers comprises one or several nanometric islands of conductingmaterial arranged between electrically insulating layers.

[0016] The transistor has a high grid-channel capacitance, due to thestack of channel layers, in other words the arrangement of the channelperpendicular to the substrate, and due to the arrangement of thegrid(s) on the flanks of the channel. Furthermore, the source—channel ordrain—channel capacitances can be made very small due to the source anddrain stack with the channel layers.

[0017] The term “conducting” used to qualify the material from whichislands are composed, is considered as being conducting in opposition todielectric materials. Therefore, it may either be a conducting materialsuch as a metal, or a semi conducting material that can form the quantumbox. The conducting material may be in the form of a continuous layer orit may be in the form of granular particles encased in an insulatingmaterial. For example, the islands may be formed from semi conductingnanocrystals (silicon) or metallic grains (aluminium).

[0018] The Coulomb blockade effect can be accentuated by putting severalquantum boxes in series, in other words by repeating the conductingmaterial /insulating material alternations in the stack of the channel.

[0019] One first process for manufacturing a transistor as describedabove could comprise the following steps in sequence, in accordance withthe invention:

[0020] deposition on an insulating substrate of a source layer, atunnel-insulating layer and an alternating stack of at least oneconducting layer and at least one insulating layer,

[0021] a first final etching of the stack to form a filiform tab,

[0022] coating of the filiform tab with an electrically insulatingcoating material,

[0023] a second final etching of the tab of the stack to form a pillar,the second etching preserving the coating material to define grooves oneach side of the pillar,

[0024] the formation of at least one grid isolated in the grooves,

[0025] the formation of a drain in contact with one end of the pillaropposite the source layer, through at least one tunnel-insulating layer.

[0026] The source and drain regions in field effect transistors areusually interchangeable. This is also true for the transistor accordingto the invention. Thus, the source layer mentioned in the process can beused as a drain and the drain formed on the stack can be used as asource.

[0027] Furthermore, the term “final etching” is used to denote etchingat the limits of the resolution of lithography techniques. The shape ofa filiform tab is the best shape for final etching. For example, tabswith a width parallel to the substrate of less than or equal to 5 nm canbe etched in the stack.

[0028] The pillar is the result of the combination of the two etchings.The two etchings preferably use filiform masks and the pillarcorresponds to a position which is covered by each of the masks insequence. The smallest dimensions for the section of the pillar areobtained when the directions of the filiform masks are perpendicular toeach other in planes parallel to the surface of the substrate.

[0029] The coating material performs three functions, firstly electricalinsulation, secondly mechanical support of the very thin pillar, andfinally formation of a mould, in fact grooves for subsequentmanufacturing of one or several grids.

[0030] The process as described above may be completed by steps, knownin themselves, for forming connection terminals for creating a contacton the grid, on the source layer and on the drain.

[0031] The grid(s) formed on each side of the pillar is (are) isolatedgrids. They are electrically isolated from the stack, but also from thevery close source and drain. For example, formation of the grid mayinclude deposition in the grooves of a grid insulating material of acontact layer and of a grid material, and then making these layers planeand stopping on the pillar.

[0032] Advantageously, planing may take place stopping on a portion of atemplate layer used as an etching mask during the first etching, andpreserved at the top of the pillar. The same material may also bepreserved in a region external to the transistor-manufacturing region tomake it easier to stop planing.

[0033] In accordance with one variant of the invention, themanufacturing process for a transistor as described above may alsoinclude the following steps in sequence:

[0034] deposition of a source layer, a tunnel-insulating layer and analternating stack of at least one conducting layer and at least oneinsulating layer, on an insulating substrate,

[0035] a first etching of the stack according to a template layer toform a strip,

[0036] coating of the strip with an electrically insulating coatingmaterial,

[0037] a second etching of the strip in the stack to form a column, thesecond etching preserving the coating material to define grooves on eachside of the column, and the second etching protecting a part of thetemplate layer on the column,

[0038] formation of at least one isolated grid in the grooves,

[0039] withdrawal of the template layer to expose part of the isolatedgrid and formation of at least one spacer extending partially on thecolumn, in contact with the isolated grid,

[0040] etching of the column, using the spacer as an etching mask, so asto preserve at least part of the column located under the spacer,

[0041] cutting of pillars in the preserved part of the column,

[0042] insulating coating of the pillars, and

[0043] formation of at least one drain in contact with at least one endof a pillar, opposite the source layer, through at least onetunnel-insulating layer.

[0044] The terms “strip” and “column” are used in contrast to “tab” and“pillar” to mean that they are not necessarily the result of finaletchings. The dimensions of the finally obtained pillars are always verysmall, are not dictated by the width of the strip or the dimensions ofthe column. At least one dimension of pillars is fixed by the width oflateral spacers formed in sequence on the grid(s). The lateral spacersmay be obtained in a manner known in itself by conform deposition of alayer of material and then anisotropic etching of this layer toeliminate all parts parallel to the surface of the substrate. The widthof the spacers, and therefore one of the dimensions of the pillars,depend on the width of the spacers, in other words particularly on theetching duration and the thickness of the deposited material layer.

[0045] Note that the process may be used by forming several pillars,several grids and several drains. Different possibilities for cuttingpillars are also proposed.

[0046] According to a first possibility, cutting of pillars in thepreserved part of the column may include:

[0047] formation of one sacrificial pad of mask material above thepreserved part of the column, with at least one flank defining an edgeof at least one pillar to be formed,

[0048] formation of at least one spacer on the flank of the sacrificialpad,

[0049] etching of the preserved part of the column, using the spacer ofthe sacrificial pad as an etching mask, to preserve the pillar under thespacer.

[0050] The spacer can define a second edge of the pillar or it canextend above the coating material.

[0051] The sacrificial pad may be used only for manufacturing spacers.In this case, it is preferably eliminated before etching of the pillars.However, the pillars stand without any lateral mechanical support untilthey are coated, and are therefore fairly fragile.

[0052] This is why according to one improvement, it is also possible tocut out pillars in two steps, including an intermediate consolidation.In this case, the etching comprises:

[0053] a first etching using the sacrificial pad and the spacer of thepad as the etching mask,

[0054] consolidation of the remaining part of the column by anelectrically insulating material,

[0055] elimination of the sacrificial pad, preserving the spacer of thesacrificial pad, and

[0056] a second etching using the spacer of the sacrificial pad as amask to define at least one pillar.

[0057] The process continues as described above by coating and isolatingthe pillars. These operations may take place by covering the freelateral faces of the pillars with an insulating material that then actsas a mechanical support and electrical insulation. For example, thematerial used could be the same as the material used for intermediateconsolidation.

[0058] Other characteristics and advantages of the invention will becomeclearer from the following description with reference to the figures inthe appended drawings. This description is given purely for illustrativepurposes and is in no way restrictive.

BRIEF DESCRIPTION OF THE FIGURES

[0059]FIG. 1 is a diagrammatic section through a substrate used formanufacture of a transistor according to the invention.

[0060]FIG. 2 is a top view of the substrate in FIG. 1.

[0061]FIG. 3 is a diagrammatic section (III-III) at a larger scalethrough a central part of the device in FIG. 2 in which a stack oflayers has been formed.

[0062]FIG. 4 is an enlarged top view of the device in FIG. 3 after afirst etching.

[0063]FIG. 5 is a top view of the device in FIG. 4 and illustrates theformation of a second etching mask.

[0064]FIG. 6 is a top view of the device in FIG. 5 after a secondetching.

[0065]FIG. 7 is a diagrammatic section through the device in FIG. 6 andillustrates an intermediate step in manufacturing an isolated grid.

[0066]FIG. 8 is a diagrammatic section through the device in FIG. 6 andillustrates completion of the isolated grid.

[0067]FIG. 9 is an enlarged top view of the device in FIG. 8 andillustrates the formation of a drain access.

[0068]FIGS. 10 and 11 are larger scale diagrammatic sections through acentral part of the device in FIG. 8 illustrating preparation of thedrain access.

[0069]FIG. 12 is an enlarged top view of the device in FIG. 11 andillustrates an additional step in the drain access.

[0070]FIG. 13 is a larger scale diagrammatic section through a centralpart of the device in FIG. 12 and illustrates manufacturing of source,drain and grid connection terminals.

[0071]FIG. 14 is an enlarged top view of the device similar to thedevice in FIG. 13.

[0072]FIG. 15 is a diagrammatic section through a substrate used formanufacturing a transistor according to the invention, according to aprocess forming a variant to the process illustrated in FIGS. 1 to 14.

[0073]FIG. 16 is a top view of the device in FIG. 15.

[0074]FIG. 17 is a larger scale diagrammatic section through a centralpart of the device in FIG. 16 on which a stack of layers has beenformed.

[0075]FIG. 18 is an enlarged top view of the device in FIG. 17 after afirst etching.

[0076]FIG. 19 is a top view of the device in FIG. 18 and illustrates theformation of a second etching mask.

[0077]FIG. 20 is a larger scale diagrammatic section through a centralpart of the device in FIG. 19 and illustrates the formation of a columnin the stack of layers.

[0078] FIGS. 21 to 24 are diagrammatic sections through the device inFIG. 19 and illustrate the manufacture of isolated grids on the flanksof the column.

[0079]FIG. 25 is a section through the device in FIG. 24 and illustratesthe formation of a first spacer.

[0080]FIG. 26 is a section through the device in FIG. 25 and illustratesa second etching of the column.

[0081]FIG. 27 is a diagrammatic section through the device in FIG. 26and illustrates a step for isolating and protecting a remaining part ofthe column.

[0082]FIG. 28 is an enlarged top view of the device in FIG. 27.

[0083]FIG. 29 is a top view of the device in FIG. 28 and illustrates astep in the formation of a sacrificial pad.

[0084]FIG. 30 is a larger scale diagrammatic section through a part ofthe device in FIG. 19 and illustrates the formation of spacers on thesacrificial pad.

[0085]FIG. 31 is an enlarged top view of the device in FIG. 30 andillustrates the withdrawal of the sacrificial pad.

[0086]FIG. 32 is a larger scale diagrammatic section of a central partof the device in FIG. 31 and illustrates a new etching for the formationof pillars in the remaining part of the column.

[0087]FIG. 33 is a diagrammatic section through the device in FIG. 32and illustrates coating of the pillars.

[0088] FIGS. 34 to 36 are diagrammatic sections through the device inFIG. 33 and illustrate preparation of the grid access on the pillars.

[0089]FIG. 37 is a diagrammatic section through the device in FIG. 36and illustrates the formation of a drain.

[0090]FIG. 38 is an enlarged top view of the device in FIG. 37 andillustrates a step for isolating and forming the contact terminals.

[0091]FIG. 39 is a top view of the device in FIG. 30.

[0092]FIG. 40 is a larger scale diagrammatic section through a centralpart of the device in FIG. 38 and illustrates etching of the columnaccording to a variant of the process in FIG. 32.

[0093]FIG. 41 is a diagrammatic section through the device in FIG. 40and illustrates a step in coating the remaining part of the column.

[0094]FIG. 42 is a diagrammatic section through the device in FIG. 41and illustrates etching of pillars.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0095] In the following description, identical, similar or equivalentparts in the different figures are marked by the same reference symbolsto facilitate comparison between the figures. Furthermore, for reasonsof clarity, not all elements are shown at the same scale.

[0096]FIG. 1 shows the structure of a substrate used for manufacturing atransistor according to the invention. It is an SOI (Silicon OnInsulator) type substrate.

[0097] The substrate comprises a layer 10 of solid silicon used as asupport, and a surface layer made of monocrystalline silicon 12, whichis of the order of 1 to 200 nm thick. The surface layer 12 is bonded tothe solid layer 10 through a buried insulating layer 14. The buriedlayer 14 may for example be a silicon oxide layer, and is of the orderof 10 to 400 nm thick.

[0098]FIG. 2, which is a top view of the substrate in FIG. 1, shows afirst etching operation of the surface layer to delimit it and to form asource of the future transistor. In the remainder of the text, reference12 is reserved for this part of the surface layer that is denoted as the“source layer”.

[0099] As shown in FIG. 3, the process is continued by the formation ofa thin tunnel-insulating layer 20, an alternating stack 22 of thinconducting layers 22 c, thin insulating layers 22 i and a so-calledtemplate layer 24, which is also insulating, on the source layer 12. Inthis example, the template layer 24 is a layer of silicon nitride.

[0100] The thin layers 22 c and 22 i are of the order of one nanometerthick, like the tunnel-insulating layer 20. For example, they may besilicon layers in continuous or granular form alternating with siliconoxide layers. The choice of materials and the thickness of the stacklayers are adapted for the subsequent formation of quantum boxes. Theyare sufficiently thin to enable electrons to pass by the tunnel effectwhen the transistor is correctly polarised.

[0101] Note that FIG. 3, which is a section along plane III-IIIindicated in FIG. 2, does not represent the entire substrate in FIG. 2,but only the central part which is the part coincident with the limitsof the source layer 12.

[0102]FIG. 4 is a top view of the device. It shows the result of a firstlithography and a final etching step. The final etching is designed toform a filiform tab 30 in the stack. The tab 30 has a width 1 in a planeparallel to the surface of the substrate which is less than 50 nm and ispreferably of the order of 5 nm. Filiform etching methods are capable ofmaking such narrow widths precisely. The pattern is dictated by anetching mask, not shown, conventionally formed by lithography. Thefiliform part of the stack is delimited by widened terminal parts 32,for which the function will be described later.

[0103] The anisotropic final etching in this example is made by stoppingon the tunnel-insulating layer 20. It may be a single etching or etchingin several steps, so as to adapt the etching agents to the differentlayers to be eliminated.

[0104] Etching may be stopped either by the choice of selective etchingagents, in other words agents that attack materials in the differentlayers with different reaction speeds, or by adjusting the layerthicknesses. Thus, a thicker layer can be used as a stop layer foretching a thinner layer even if the selectivity of the etching agents isnot very good.

[0105] In this example, the tunnel-insulating layer 20 is not very thickand therefore does not form a very good etching stop layer. However, asdescribed in the remainder of the text, penetration of this layer duringetching does not prevent correct operation of the transistor.

[0106]FIG. 5 shows the formation of an electrically insulating coatinglayer 40. For example, it may be a glass or silicon oxide layerdeposited on the entire substrate. It coats and covers the tab 30 thathas just been etched in the stack in a conform manner.

[0107] The coating layer is planed, for example by polishing, stoppingon the template layer 24. Planing results in a plane upper face on whichthe template layer is exposed at the top of the stack.

[0108] A discontinuous line indicates the limits of the source layer 12.

[0109] As also shown in FIG. 5, a second filiform etching mask 42 isthen formed on the top face of the device. Like the mask that was usedto etch the tab previously, the mask 42 is a filiform mask, for examplea resin mask not more than 50 nm wide. The second etching mask is placedso as to cross the filiform tab 30 of the stack and preferably to crossit approximately perpendicular to it.

[0110] After formation of the mask, the substrate is subjected to asecond final etching. The second etching is also a selective anisotropicetching that eliminates the stack outside the small region protected bythe second mask 42. The stack is etched again stopping on thetunnel-insulating layer 20. FIG. 6 shows the device obtained afterwithdrawal of the second etching mask.

[0111] All that remains of the stack of layers is a pillar 50. Thepillar 50 is placed in the middle of a groove 52 for which the sidewalls are formed by the flanks of the coating layer 40, exposed duringthe second etching. The grooves open up into wells 54, also called gridwells, the location of which corresponds to the enlarged end parts ofthe stack.

[0112]FIG. 7 is a section through the device in FIG. 6 along the groove52, and shows the formation of isolated grids 60 in the groove. Forreasons of simplification and clarity in the figure, the central part isshown at a larger scale. Similarly, the groove 52 is shown shorter thanit really is and the grid wells are not shown. Since the groove extendsfrom one side of the pillar to the other, it can be considered that thetransistor has two grids. It can also be considered that it is a singlegrid in two parts to which identical polarisation voltages may or maynot be applied during operation.

[0113] The formation of isolated grids includes the successivedeposition of a layer of grid insulation 62, followed by one or severallayers of grid material. In the example illustrated, the deposition ofthe grid insulation, for example silicon oxide, is followed by theformation of an additional conducting layer of grid material that can beoxidised at low temperature, for example titanium nitride 64 and a layerof polycrystalline silicon 66. The titanium nitride increases theconductivity of the grids.

[0114] Other grid materials that can be oxidised at low temperature canbe used; “Midgap” materials (TiN, W), n⁺ type materials (Sipoly, Nb) orp⁺ type materials (Sipoly, Ni).

[0115] However, the additional layer 64 is not indispensable.

[0116] Layers are deposited in a conform manner, for example obtained bya chemical vapour deposition (CVD) process. In other words, the layersuniformly cover the bottom of the groove, cover the pillar 50 and coverthe coating layer 40, part of which is shown on the edges of the figure.

[0117] The global thickness of the layers is sufficient to entirely fillin the groove 52.

[0118] Note that the electrical insulation of the grids with respect tothe pillar 50, and also with respect to the bottom of the groove, isachieved by the layer of grid insulating material. Thus, a short circuitbetween the source layer 12 and the grids is avoided when one of theprevious etchings has penetrated the tunnel-insulating layer at thebottom of the grooves, in other words if the etching stop wasinsufficiently selective. Thus, operation of the transistor is notcompromised.

[0119] Manufacturing of the grids is followed by planing of thepreviously deposited layers. For example, this may be amechanical-chemical polishing made stopping on the coating layer and onthe template layer at the top of the pillar. Dummies previously etchedin the stack of layers covered by the template layer 24 could beprovided outside the transistor-manufacturing region, to facilitatestopping planing. This type of dummy is not shown in the figures.

[0120]FIG. 8 shows the grids obtained at the end of planing. They areexposed on the plane of the free surface of the coating layer 40. Anelectrically insulating surface layer 68 is formed on the surface of thegrids. For example, it may be an oxide layer obtained by the oxidationof layers of grid material 66 (and the additional layer 64).

[0121]FIG. 9 shows the formation of an etching mask 70 on the free faceof the device in FIG. 8. The etching mask 70, for example made of resin,is shaped using usual lithography techniques to define an opening 72 init. The opening is aligned approximately on the region of the device inwhich the pillar 50 is located. Preferably, the dimensions of theopening are larger than the dimensions of the pillar parallel to thefree face of the device. Thus, the alignment of the opening on thepillar is not a critical operation.

[0122]FIG. 10, which is a section comparable to the section in FIG. 8,gives a better view of the relative position of the opening of the mask70 and the pillar 50. The pillar is etched through the opening of themask. The etching eliminates the template layer (ref. 24 in FIG. 8) andall or some of a subjacent insulating layer if there one (22 i, FIG. 3).

[0123] Note that the template layer may also be eliminated by selectiveetching with respect to the materials exposed on the surface of thedevice, in fact the electrically insulating surface layer 68 of thegrids and the coating layer 40. In this case, the mask formation stepillustrated by FIG. 9 is useless.

[0124] However, use of the mask enables a wider choice of materials andetching agents for the template layer. Different forms of holes can beobtained depending on the degree of selectivity in the attack of thedifferent layers. In some cases, it may be advantageous to reduce theaspect ratio of the hole. For example, etching of the differentmaterials at approximately equivalent speeds can result in faceting, inother words the formation of facets 74 on the corners of isolated grids,exposed in the opening of the mask. This is shown in FIG. 10.

[0125]FIG. 11 shows an additional optional step consisting ofreoxidising facets at the corners of the exposed isolated grids. Thisoperation prevents conducting layers in the grid from becoming exposed.

[0126] The oxidation preferably takes place before the template layer 24is removed. Furthermore, although the presence of the mask 70 is useful,it is not indispensable. The materials in layers 62, 64, 60, 66 can beoxidised under conditions such that the corners are rounded before thelayer 24 is eliminated.

[0127] The oxidation operation of the grid material may take placebefore the template layer 24 is etched, for example in the case in whichselectivity with respect to other materials is infinite (no faceting).It may also take place after etching of the template layer 24,particularly when selectivity is not infinite. Finally, oxidation cantake place before and after etching of the template layer 24.

[0128] For guidance, FIG. 11 shows the limits of the isolated grids thatresult from a perfectly selective etching of the template layer.

[0129] The next step, also optional and illustrated in FIG. 12, consistsof selectively eliminating a sacrificial isolating surface layer at thetop of the pillar, that was exposed by prior elimination of the templatelayer. This selective etching step exposes a conducting layer 22 c inthe stack of the pillar 50.

[0130]FIG. 13 shows the formation of an isolated drain 80 in the wellopened by etchings described with reference to FIGS. 9 to 12. Itcomprises deposition of tunnel-insulating layer 82 made of a siliconoxide followed by a conducting layer 84, for example made of metal.These layers are shaped to fix the extension of the isolated drain abovethe electrically insulating surface layer 68.

[0131] The fact of making the upper tunnel junction 82 after theessential part of fabrication of the Coulomb blockade transistoraccording to the invention rather than during manufacture of thealternating stack 22, defined by horizontal and vertical cross etchingsshown in FIGS. 4 and 5 respectively, is important. This enables precisecontrol over the thickness and characteristics of this tunnel junctionsuch as its crystalline quality, its physicochemical qualities and theinterface. There is no risk of inducing secondary effects that couldappear during intermediate steps that take place between deposition ofalternating layers of the stack (FIG. 3) and making the upper electrode80 (FIG. 13). Steps subsequent to the steps described in FIG. 13 are endof process steps that involve lower temperatures and that induce lessimportant secondary effects.

[0132] In particular, the process according to the invention enablesfine adjustment of the thickness of tunnel junctions.

[0133] The surface-insulating layer 22 i of the pillar can be used as atunnel insulation for the drain. However, since this layer has alreadybeen used as an etching stop layer for the template layer, its thicknessmay be modified by accidental over etching. The fact of eliminating thislayer in the manner suggested in FIG. 12 and replacing it by the newtunnel-insulating layer 82 reduces the risk of accidental direct contactbetween the drain and a pillar island.

[0134] Accessorily, FIG. 13 also shows “encapsulation” of thetransistor. A covering material 90, such as undoped silicon oxide, orborophosphosilicated glass, is deposited on the transistor so as toentirely cover the drain 80. The material is then planed to make itsouter surface plane. Access wells are etched in the covering material 90vertically in line with at least one grid, the drain and part of thesource layer extending beyond the pillar. The wells are filled with atleast one conducting material such as W, TiN, Ti to form accessterminals to the grid, drain and source. The terminals are marked withreferences 92, 94 and 96 respectively in FIG. 13.

[0135]FIG. 14 is a top view of the transistor after “encapsulation”. Itshould be noted that the source connection terminal 96 has been broughtinto the plane of the section in FIG. 13, to simplify the drawing. Thereal arrangement of this terminal can be seen in FIG. 14.

[0136]FIG. 14 shows a minor variant embodiment of the device and showsthe drain terminal 94, the source terminal 96 and two grid terminals 92a and 92 b. The two grid terminals correspond to the two parts of thegrid on each side of the channel. It can also be observed that the drainterminal 94 is not necessarily above the drain or the pillar, but it maybe offset laterally. Finally, the grid terminals 92 a and 92 b are notformed on the filiform parts of the grids, but at their widened ends.

[0137] FIGS. 15 and subsequent figures described below illustrateanother possibility for making a transistor conform with the invention,in other words a transistor with a vertical channel and Coulombblockade.

[0138] The manufacturing steps illustrated in FIGS. 15, 16 and 17 areidentical to those already described with reference to FIGS. 1 to 3.Thus, refer to the above description.

[0139]FIG. 18 corresponds to FIG. 4. It illustrates a first etching ofthe stack of layers stopping on the tunnel-insulating layer 20. However,the first etching is not an final etching in the process illustrated inFIG. 18. It can be observed that the thin tab of the stack in FIG. 4 isa wider band 31 on FIG. 18. The width of the strip 18 may for example bebetween 100 and 300 nm. Its ends, like the ends of the tab in FIG. 4,are widened. The outer part of the strip 31, after elimination of anetching mask not shown, is formed by the template layer 24.

[0140]FIG. 19 shows coating of the stack shaped after the first etching.The figure shows the placement of a coating layer 40 of an electricallyinsulating material and the formation of a second etching mask 42. Thissecond mask is also wider than the second mask described with referenceto FIG. 5. Its width is of the same order of magnitude as the width ofthe strip 31 formed in the stack.

[0141] A second etching, which is not a final etching, forms a column 51for which the location corresponds to the intersection of the secondmask with the strip 31. Except for its dimensions, the column 51 is verysimilar to the pillar 50 described with reference to FIGS. 6 and 7.

[0142]FIG. 20 is a diagrammatic section through a central part of thedevice in FIG. 19, and shows the column 51 at larger scale. The column51 includes an alternating stack 22 of insulating layers 22 i and“conducting layers” 22 c and the template layer 24. The insulating layer22 i that is immediately under the template layer is a sacrificial layerthat can possibly be replaced in the remainder of the process by anothertunnel insulating layer.

[0143] Reference 52 once again denotes a groove that extends from oneside of the column to the other.

[0144]FIG. 21 illustrates the deposition of a grid-insulating layer 62that covers the column 51 and the tunnel-insulating layer 20 at thebottom of the grooves, in a conform manner. For example, it may be asilicon oxide layer of the order of 8 nm thick. In the same way as thegrid-insulating layer 62 that can be seen in FIG. 7, it can overcome apossible fault or over etching of the tunnel-insulating layer 20.

[0145] The deposition of the grid-insulating layer 62 is continued bydeposition of one or several grid materials. In the example in FIG. 22,a layer 66 of titanium nitride, polycrystalline silicon or another gridmaterial of the “Midgap”, N⁺ or P⁺ type is deposited. Like the processdescribed with reference to FIG. 7, the grid 60 may also be formed fromtwo or more conducting or semi-conducting layers.

[0146] As shown in FIG. 22, the total thickness of the layers depositedfor the formation of isolated grids is sufficient to fill in the groove52 entirely.

[0147] Planing, for example done by mechanical-chemical polishing, isintended to make the upper surface of the structure plane where thetemplate layer 24 made of silicon nitride is exposed. This is located atthe top of the column 51. The template layer, and any dummies not shown,are used as planing stops, such that the grid-insulating layer iseliminated above the template layer.

[0148]FIG. 24 shows the formation of an electrically insulating surfacelayer 68 at the surface of the grids 60. This may be formed simply bysurface oxidation of the grid material.

[0149]FIG. 25 shows a step consisting of eliminating the template layerabove the column 51 by selective etching. This etching exposes aninsulating surface layer 22 i in the stack, also considered as beingsacrificial.

[0150] After etching, spacers 63 are formed on the flanks of thegrid-insulating layer 62. These are flanks vertically in line with thesurface-insulating layer 22 i and exposed during elimination of thetemplate layer.

[0151] Conventionally, formation of the spacers includes the depositionof an electrically insulating material such as silicon oxide, forexample, followed by anisotropic etching of this material until it isfully eliminated on the faces parallel to the substrate layers.

[0152] The lateral extension of spacers 63 above the column 51 may beadjusted to very low values of the order of a few nanometers. This smalloverlap is used as an etching mask for a subsequent anisotropic etching.

[0153] The result of final etching done in this example, stopping on thetunnel-insulating layer 20 that covers the source layer 12, isillustrated in FIG. 26. The lateral extension of the spacers 63 ischosen to be just sufficient to not entirely eliminate layers of thestack under the spacers. The remaining part of the column under thespacers is comparable to two small walls shown in section in FIG. 26.

[0154] The depression formed by the etching between the grids is filledin by a block of insulating material shown in FIG. 27. Preferably it isan oxide block, such as silicon oxide formed by deposition and thenplaning.

[0155]FIG. 28 is a more global top view, showing the relative layout ofthe coating material 40, the surface-insulating layer 68 covering thegrids, the oxide block 69 and the grid-insulating layer 62 flanked byspacers 63.

[0156]FIG. 29 shows the formation of a sacrificial layer 100 on theupper face of the device in FIG. 28. For example, it may be apolysilicon layer.

[0157] A resin mask 102 is formed on the sacrificial layer. This is amask extending from one side of the oxide block 69 to the other, andspacers 63, going as far as above the grids 60. The mask 102 ispreferably centred with respect to the extension of the spacers 63perpendicular to the strip 31. It is also slightly narrower than thestrip 31 mentioned with reference to FIG. 20, in other words slightlynarrower that the spacers 63.

[0158] The resin mask is used as an etching mask to shape thesacrificial layer 100.

[0159] After etching the sacrificial layer, the result is a sacrificialpad that is marked with the same reference 100 as the layer, forconvenience reasons.

[0160]FIG. 30 is a section XXX-XXX through the device in FIG. 29 along aspacer 63. It shows the remainder of the column 51, in other words thesmall wall of the initial stack remaining under the spacer, and therelative position of the sacrificial pad 100. The sacrificial pad inthis case is seen in section after elimination of the resin mask.

[0161]FIG. 30 also shows that the lateral flanks of the pad are alsolined with spacers 104. For example, these spacers may advantageously bemade of silicon oxide, SiC or TiN, also formed by deposition thenanisotropic etching of the material. The pad dimensions are adjustedsuch that the pad spacers 104 are arranged above the spacers 63 of thegrid insulation, by crossing them.

[0162]FIG. 31 shows a top view of the device after selective eliminationof the sacrificial pad and more clearly shows the crossing of thespacers 63 and 104.

[0163] After the sacrificial pad has been eliminated, the next step is anew selective etching of the stack layers, and more precisely of theremainder of the column 51, using the spacers 104 of the sacrificial padas an etching mask. During this etching, the unprotected parts of thespacers 63 of the grid-insulating layer are also eliminated. The coatinglayer 40 is always kept. The result of this etching can be seen in FIG.32 that corresponds to the same section plane as FIG. 30. It releasesfour pillars 50, only two of which are visible in the figure.

[0164] An oxide deposit 108 followed by planing consolidate the pillarswhile electrically insulating them. These operations are illustrated inFIG. 33.

[0165]FIG. 34 illustrates selective etching to eliminate the spacer 104from the sacrificial pad and the subjacent part of the spacer 63 in thegrid-insulating layer. Limited selectivity of etching results in flaredwells 110 above the pillars 50.

[0166] As in the previous embodiment, it is preferable to preciselycontrol the thickness of the tunnel-insulating layer that separates thedrain from the channel.

[0167] This is done by eliminating a possible surface-insulating layerin the pillar stack to expose one of the thin conducting layers 22 c. Inthe example illustrated, the objective will be to eliminate theinsulating layer at the top of the stack and considered to besacrificial, as shown in FIG. 35. Note that when the last insulatinglayer at the top of the pillars is to be replaced, it can be madeslightly thicker than the other layers of the stack to make it the bestetching stop layer for the formation of wells 110.

[0168]FIG. 36 shows the deposition of a new tunnel-insulating layer 82for which the thickness is perfectly controlled to form a tunneljunction above the conducting layer 22 c of the previously exposedpillars. The tunnel insulating layer, for example a layer of SiO₂,extends in the flared wells, and if applicable, onto the oxide layer 108formed for mechanical consolidation of the pillars 50.

[0169]FIG. 37 shows the formation of a drain by deposition and thenformation of a conducting layer 84.

[0170] The assembly composed of the tunnel-insulating layer 82 and theconducting layer 84 forms an isolated drain marked by reference 80, byanalogy with FIG. 13.

[0171] In the example illustrated, a single isolated drain is associatedwith the four transistor channels corresponding to the four pillars 50.However, the drain can be split into two or four mutually isolateddrains to form four transistors with a common source. However, the samegrid is associated with two channels each time, and therefore with twotransistors.

[0172]FIG. 38, like FIG. 14 described above, shows the transistorobtained after “encapsulation” under a cover layer (90). The figureshows a drain terminal 94 connected to the four pillars 50, and a gridterminal 92 a associated with the grid of the left pillars in thefigure, and a grid terminal 92 b associated with the grid of the rightpillars in the figure, and a source connection terminal 96.

[0173] We will now describe a variant of the above process that includesall steps described with reference to FIGS. 15 to 30 identically.

[0174]FIG. 39 is a top view of the device in FIG. 31. It shows that thesacrificial pad is not eliminated, unlike the process in FIG. 32.

[0175] A selective anisotropic etching of the remaining part of thecolumn takes place using the sacrificial pad 100 and the lateral spacers104 of the pad as etching masks. Etching, stopping on thetunnel-insulating layer 20, cuts out a small wall 49 in the remainingstack as shown in FIG. 40. FIG. 40 is a section XXX-XXX through thedevice in FIG. 39 along one of the spacers 63.

[0176]FIG. 41 shows consolidation of the small wall by an insulatinglayer 108 a, for example made of an oxide. This operation is followed byelimination of the sacrificial pad and by a new selective anisotropicetching. The second etching only uses the spacers 104 of the sacrificialpad 100 as an etching mask. The result is then pillars 50 identical tothose in FIGS. 32 and 33.

[0177] As shown in FIG. 42, these pillars are consolidated by a newinsulating layer 8 b. Finally, the layers 108 a and 108 b perform thesame function as layer 108 in FIG. 33.

[0178] The variant described herein and that is equivalent to etchingpillars in two steps with an intermediate mechanical stiffening, largelyreduces the risk of accidental breakage of the pillars that have a smallcross section.

[0179] Documents Mentioned

[0180] (1) “Fabrication and electron transport in multilayersilicon-insulator-silicon nanopillars”

[0181] David M. Pooley and Haroon Ahmed

[0182] J. Vacc. Sci. technol. B 17 (No.6), Nov/Dec 1999, pp. 3235-3238

[0183] (2) “Enhancement of Coulomb Blockade and tunability by multidotcoupling in a silicon-on-insulator-based single-electron transistor”

[0184] J. W. Park, K. S. Park, B. T. Lee, C. H. LEE, S. D. Lee and JungB. Choi

[0185] APPLIED PHYSICS LETTERS, Vol. 75, No. 4, 26 Jul. 1999, pp.566-568

[0186] (3) “Coulomb Blockade in silicon nano-pillars”

[0187] D. M. Pooley and H. Ahmed

[0188] APPLIED PHYSICS LETTERS, vol. 74, No. 15, 12 Apr. 1999, pp.2191-2193

1. Coulomb blockade transistor comprising the following on a substrate:a stack of channel layers (22, 22 i, 22 c) forming at least one quantumbox, a source (12) and a drain (80) connected to the quantum box throughtunnel junctions, at least one of which is distinct from the layers ofthe stack, and stacked with the channel layers, at least one grid (60)facing at least one flank of the stack, the stack of channel layerscomprising at least one nanometric conducting island (22 e) arrangedbetween electrically insulating layers (22 i).
 2. Transistor accordingto claim 1, in which the island (22 c) is formed from a continuous layerof conducting material.
 3. Transistor according to claim 1, in which theisland (22 c) is formed by a layer of granular conducting particlesencased in an insulating material.
 4. Process for manufacturing aCoulomb blockade transistor comprising the following on a substrate: astack of channel layers (22, 22 i, 22 c) forming at least one quantumbox, a source (12) and a drain (80, 82, 84) connected to the quantum boxthrough tunnel junctions, at least one of which is distinct from thelayers of the stack, and is stacked with the channel layers, at leastone grid (60) facing at least one flank of the stack, the stack oflayers comprising at least one nanometric conducting island (22 c)arranged between the electrically insulating layers (22 i), the processcomprising the following steps in sequence: deposition on an insulatingsubstrate of a source layer (12), a tunnel-insulating layer (20) and analternating stack of at least one conducting layer (22 c) and at leastone insulating layer (22 i), a first etching of the stack to form afiliform tab (30), coating of the filiform tab with an electricallyinsulating coating material (40), a second etching of the tab of thestack to form a pillar (50), the second etching preserving the coatingmaterial (40) to define a groove (52) on each side of the pillar (50),the formation of at least one isolated grid (60) in the groove (52), theformation of a drain (84) in contact with one end of the pillar oppositethe source layer, through at least one tunnel-insulating layer (82). 5.Process according to claim 4, also including the formation of connectionterminals (92 a, 92 b, 94, 96) on the source layer, the grid, and thedrain.
 6. Process according to claim 4, in which formation of theisolated grid includes deposition of a grid-insulating material (62),and a grid material (66) in the groove (52), and then making theselayers plane and stopping on the pillar.
 7. Process according to claim6, in which the first final etching is done following a template layer(24) and at least one portion of the template layer (24) is kept on thepillar during the second final etching, and in which planing takes placeon the portion of the template layer.
 8. Process for manufacturing aCoulomb blockade transistor comprising the following on a substrate: astack of channel layers (22 c, 22 i, 22 c) forming at least one quantumbox, a source (12) and a drain (80) connected to the quantum box throughtunnel junctions, at least one of which is distinct from the layers ofthe stack, and stacked with the channel layers, at least one grid (60)facing at least one flank of the stack, the stack of channel layerscomprising at least one nanometric conducting island (22 c) arrangedbetween electrically insulating layers (22 i). the process comprisingthe following steps in sequence: deposition of a source layer (12), atunnel-insulating layer (26) and an alternating stack of at least oneconducting layer (22 c) and at least one insulating layer (22 i), on aninsulating substrate, a first etching of the stack according to atemplate layer (24) to form a strip (31), coating of the strip with anelectrically insulating coating material (40), a second etching of thestrip (31) in the stack to form a column (51), the second etchingpreserving the coating material (40) to define a groove (52) on eachside of the column (51), and the second etching protecting a part of thetemplate layer (24) on the column (51), formation of at least oneisolated grid (60) in the groove (52), withdrawal of the template layer(24) to expose part of the isolated grid and formation of at least onespacer (63) extending partially onto the column (51), in contact withthe isolated grid, etching of the column (51), using the spacer (63) asan etching mask, so as to preserve at least part of the column (51)located under the spacer, cutting of pillars (50) in the preserved partof the column, isolating the pillars, and formation of at least onedrain (84) in contact with at least one end of a pillar, opposite thesource layer, through at least one tunnel-insulating layer (82). 9.Process according to claim 8, in which cutting of pillars (50) includes:formation of a sacrificial pad (100) of mask material above thepreserved part of the column, with at least one flank located above anedge of at least one pillar to be formed, formation of at least onespacer (104) on the flank of the sacrificial pad (100), etching of thepreserved part of the column (51), using the spacer of the sacrificialpad as an etching mask, to preserve at least one pillar (50) under thespacer.
 10. Process according to claim 9, in which the sacrificial pad(100) is eliminated before etching of the preserved part of the column(51).
 11. Process according to claim 9, in which etching of thepreserved part of the column comprises: a first etching using thesacrificial pad (100) and the spacer (104) of the pad as the etchingmask, consolidation of the remaining part of the column by anelectrically insulating material (108 a), elimination of the sacrificialpad (100), preserving the spacer (104) of the sacrificial pad, and asecond etching using the spacer (104) of the sacrificial pad as a maskto define at least one pillar (50).